1. Field of the Invention
The present invention relates to a phase lock loop, and more particularly, to a phase-lock loop with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery.
2. Description of Related Art
Phase lock loops are common circuits used in electronic circuits for frequency synthesis, duty-cycle enhancement, and clock de-skewing. A preferred embodiment of the invention utilizes a PLL in a video-graphics analog-to-digital conversion circuit. Currently most personal computers utilize video cards that convert digital signals into RGB analog signals for displaying graphics on CRT monitors. It is therefore necessary for flat-panel displays to be able to interface with current video graphics systems. FIG. 1 shows a typical computer-flat-panel configuration. The flat-panel display requires an analog interface 30 to change the analog RGB signals into the digital signals required by the display. Computer graphics cards use RAMDACs which are configured at a pixel rate based on the resolution of the screen to convert the digital signals from the computer into an analog 256-level pulse amplitude modulated signal which are transmitted along with timing signals to the analog interface 30. The analog interface receives the analog graphics data and uses ADCs to convert the data back into a digital format. In order for this to occur though the interface must recover the original pixel clock frequency and phase correctly using a clock regenerator. The clock regenerator recreates the pixel clock by using a frequency-multiplying PLL utilizing an HSYNC signal as the reference frequency. The outputted signal from the clock regenerator is then outputted to the ADCs, and the graphics controller 40.
Many current circuits for this application use an analog PLL consisting of a voltage controlled oscillator VCO. In an application for capturing analog RGB signals and digitizing them for display on a flat-panel monitor the current designs have many limitations. The HSYNC signal used as a reference signal for pixel clock recovery is not a jitter-free signal where the amount of jitter on the signal will depend on the type of graphics card used in the computer. Most analog PLL deal with this jitter by narrowing the loop bandwidth, however this also makes it difficult to correct long term jitter effects. Further in a composite HSYNC format the VSYNC signal is embedded onto the HSYNC signal. To compensate for HSYNC variations caused by the VSYNC signal the PLL will coast, or in other words attempt to keep the control voltage for the VCO at a constant level. However in an analog PLL design often the control voltage will undesirably drift due to leakage, causing an unacceptable xe2x80x9ctearingxe2x80x9d effect often seen in the top left-hand corner of the display. In order to keep PLL loop stability at a maximum many designs make use of large off-chip loop filter capacitors. These components however are very susceptible to external noise interference.
Further most conventional phase detectors used in PLL are binary early/late in digital case, or up/down pulse width in analog systems. Binary PLL leads to an ambiguity of 1 clock signal during phase acquisition. To exemplify with reference to FIG. 3, when the rising edge of the REF_CLK occurs between the rising edges of clocks 0 and 1 of the DCO_CLK, the system is unable to determine which DCO_CLK rising edge the REF_CLK rising edge is closest too. The system may therefore select the signal shown in Ex. 1 or in Ex. 2., however as can be seen T1 less than T0 hence Ex. 2 is the more accurate timing signal. This ambiguity can slow down phase acquisition, or even cause temporary loss of lock in some cases.
A further limitation of complex analog PLL is the difficulty in implementing its design into a low cost CMOS process.
Therefore a need exists for a PLL that can be used in low cost CMOS process, can compensate for reference signal jitter, has fast phase acquisition, and can maintain a stable frequency during a coast period due to a VSYNC signal.
It is therefore an object of the present invention to provide a Phase Lock Loop with intelligent phase detection and correction, allowing phase acquisition to occur quickly and accurately.
It is another object to provide a PLL with a stable output frequency during reference signal fluctuations, and post-freerun fast phase recovery.
It is another objective to provide a PLL with high immunity to clock jitter whether it be reference signal jitter, or system noise.
It is an object to provide a PLL that can be easily incorporated into a low cost CMOS process.
To further accomplish these and other objects of the present invention, a novel PLL structure architecture is utilized. The PLL is composed of an intelligent phase detector that can more accurately determine the position of a rising edge of an input signal for faster phase acquisition. As well the phase detector in combination with a lock detector determines the correct operational codes sent to a loop filter which utilizes digital signal processing to control the frequency of a digitally controlled oscillator. The DCO as described in a co-pending application has high immunity to signal jitter and noise. Utilizing a DCO in the design has the further advantage of easily and solidly locking the output frequency at a required value during a HOLD condition. The output of the oscillator is counted and compared with the input signal. The invention also provides an improved method for maintaining output clock stability during input reference signal flucuations. A coast signal is applied issuing a HOLD condition in the loop filter and DCO. After the input reference signal fluctuations have ended, the coast signal is removed and a phase booster allows for faster phase reacquisition.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.